1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a pad in a semiconductor device and a fabricating method thereof.
2. Discussion of the Related Art
Generally, a pad is an element mandatory for MMIC (Micro-wave Monolithic Integrated Circuit) or RFIC (Radio Frequency Integrated Circuit) using semiconductor devices. A pad in a semiconductor device is necessary for signal input/output, for measuring characteristics of the device directly, and/or for wire bonding in the case of packaging a fabricated integrated circuit (IC). Namely, the semiconductor device pad plays a role in transferring a signal or supplying a power (or transferring a power) to or from the IC.
A general pad in a semiconductor device is explained with reference to the accompanying drawings as follows.
FIGS. 1A to 1C are diagrams of general pads in semiconductor devices.
First of all, structures of the above pads, which are disclosed in detail in pp. 203˜306 of “Ultra Low-capacitance Bond Pad for RF application in CMOS Technology,” by Yun-Wen Hsiao et al., are schematically explained as follows.
Referring to FIG. 1A, a general pad consists of a ground metal or a semiconductor substrate electrode 10, metal electrodes M6 to M8 for real measurement probing or wire bonding, and an insulating layer of Si3N4 or SiO2 between the two electrodes. Since the above structure configures a series of MIM (metal-insulator-metal) capacitors, unnecessary parasitic capacitance is generated in designing an AC integrated circuit. If the parasitic capacitance is not considered in designing an integrated circuit, the integrated circuit may malfunction. Accordingly, many efforts have been made to research and develop methods of reducing parasitic capacitance of a bond pad or a probe pad.
The pad structures shown in FIG. 1B and FIG. 1C are developed to reduce the parasitic capacitance.
Referring to FIG. 1B and FIG. 1C, the structures attempt to reduce parasitic capacitance in a manner of providing a series of spiral inductors M1 to M5 with a single layer or multiple layers under the pad. However, the spiral inductor inserted to reduce the parasitic capacitance may affect a circuit adjacent to the inductor or a neighboring pad. Therefore, in the case of using the general pad, an integrated circuit may have characteristics different from those of the original design.